License the IP. Define Your Silicon Program.
JSA LAABS licenses proprietary semiconductor intellectual property under defined commercial agreements. Our licensees retain complete control of their product architecture, software stack, and downstream manufacturing programs.
The 6-Step Licensing & Integration Process
A structured path from initial workload assessment to successful silicon bring-up.
Initial Architectural Discussion
We conduct a preliminary technical alignment to understand the customer’s target application, workload characteristics, performance targets, and overall SoC compute topology.
High-level product briefs & architectural suitability review.
Technical Evaluation (Under NDA)
Under a formal non-disclosure and evaluation agreement, qualified engineering teams gain access to simulation models, detailed register documentation, and evaluation testbenches.
Cycle-accurate simulation models, microarchitectural specs & FPGA bitstream demo.
Commercial IP Licensing
We negotiate and execute a definitive IP license agreement defining the scope of rights (single-project, multi-use, or architectural variant), commercial fees, and royalty structures.
Executed IP License Agreement & deliverable milestone schedule.
Integration Engineering Support
JSA LAABS provides agreed engineering advisory during front-end SoC integration: bus wrapper configuration, memory compilation sizing, and verification testbench co-simulation.
Synthesizable RTL drops, SDC timing constraints & verification test suites.
Customer Downstream Silicon Program
The customer and its chosen semiconductor implementation partners retain full responsibility for physical synthesis, timing closure, DRC/LVS, tapeout, and foundry manufacturing.
Licensee GDSII signoff, wafer fabrication, packaging & qualification.
Ongoing Maintenance & Architecture Evolution
Where agreed, JSA LAABS delivers maintenance updates, bug fixes, integration advisory for subsequent tapeouts, and access to roadmap architectural enhancements.
Quarterly maintenance releases, patch updates & technical support tickets.
Flexible Licensing Structures
We adapt our licensing agreements to meet the commercial scale of early-stage ASIC startups, established semiconductor vendors, and defence electronics contractors.
Single-Program IP License
Grants the licensee the right to incorporate NeuroCore IP into a single designated silicon product or chiplet architecture.
Multi-Program / Platform License
Designed for fabless semiconductor companies deploying NeuroCore across an entire product family or generation of compute silicon.
Custom IP & Co-Development
For partners with specialized architectural needs requiring customized MIMD clusters, specialized arithmetic precision, or proprietary memory topologies.
Clear Separation of Responsibilities
Understanding who does what ensures smooth engineering collaboration and rapid silicon execution.
JSA LAABS (IP Licensor)
- ✓Processor microarchitecture, execution pipelines, and instruction flow
- ✓Synthesizable SystemVerilog / Verilog RTL deliverables
- ✓Verification suites, regression coverage & golden reference models
- ✓Implementation methodology guidelines, SDC constraints & timing scripts
- ✓Front-end integration advisory & technical review meetings
Licensee (Silicon Developer)
- ✓Product-level specification, system architecture & application firmware
- ✓Host processor selection, system bus fabric, and top-level clock/power trees
- ✓Full-chip physical design (P&R), CTS, timing signoff, DRC/LVS closure
- ✓Foundry tapeout coordination, wafer fabrication, and mask tooling costs
- ✓Packaging, post-silicon testing, environmental qualification & volume shipping
Request a Technical Evaluation Agreement
Before committing to a production license, qualified semiconductor teams can evaluate NeuroCore under an evaluation license. Test representative workloads, profile latency, and review RTL quality.